By Pettit, Brinker
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Extra info for Use Of Sol-Gel Thin Films In Solar Energy Applications
5V ATtiny15/L PB5 (RESET) GND VCC PB2 SCK PB1 MISO PB0 MOSI For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the program and EEPROM arrays into $FF. The program and EEPROM memory arrays have separate address spaces: $0000 to $01FF for Program memory and $000 to $03F for EEPROM memory. 6 MHz). The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles Low-voltage Serial Programming Algorithm When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK.
Port B is a 6-bit bi-directional I/O port. Three data memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18, Data Direction Register – DDRB, $17, and the Port B Input Pins – PINB, $16. The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. 0 have special functions as described in the section “Pin Descriptions” on page 4. If PB5 is not configured as External Reset, it is input with no pull-up or as an open-drain output.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 4 – RES: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bits in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled.