Download Robust Computing with Nano-scale Devices: Progresses and by Chao Huang (auth.), Chao Huang (eds.) PDF

By Chao Huang (auth.), Chao Huang (eds.)

Although complementary metal-oxide semiconductor (CMOS) know-how will proceed dominating the electronic digital circuits for the subsequent 10-15 years, a few grand demanding situations have emerged because the transistor measurement scales down. The emerging expenses of semiconductor masks and fabrication pose financial obstacles to lithography. The quantum results and lengthening leakage strength commence surroundings actual limits on non-stop CMOS characteristic measurement shrinking.

The study advances of cutting edge nano-scale units have created nice possibilities to surpass the limitations confronted by means of CMOS expertise, which come with nanowires, carbon nanotube transistors, programmable molecular switches, resonant tunneling diodes, quantum dots, etc.

However, the good fortune of many nanotechnologies is determined by the self-assembly fabrication approach to manufacture circuits. The stochastic self-assembly fabrication, regrettably, has low reliability with illness densities a number of orders of importance better than traditional CMOS technology.

Robust Nano-Computing specializes in numerous problems with strong nano-computing, defect-tolerance layout for nano-technology at varied layout abstraction degrees. It addresses either redundancy- and configuration-based tools in addition to fault detecting recommendations during the improvement of actual computation versions and instruments. The contents current an insightful view of the continuing researches on nano-electronic units, circuits, architectures, and layout equipment, in addition to offer promising instructions for destiny research.

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Extra resources for Robust Computing with Nano-scale Devices: Progresses and Challenges

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1 Fig. 4 Gate reliability comparison between quadded-transistor structure (Q) and complementary CMOS T1 TN+1 T2 TN+2 TN2–N+1 TN T2 N TN2 Fig. 5 Defect-tolerant N2 -transistor structure composed of N blocks connected in series with each block composed of N parallel transistors, as shown in Fig. 5. N 1/ in the structure. Hence, a large number of multiple defects can be tolerated in a circuit implemented based on these structures. Furthermore, it can be shown that the probability of failure for an N2 -transistor structure is O P N assuming a transistor-defect probability, P .

32. , “Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation”, in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 207–213, 2007. 33. , Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, 1st Edition, Springer, 2008. 34. , “Fault-tolerant techniques for nanocomputers,” Nanotechnology, vol. 13, 2002, pp. 357–362. 35. , “Error detection by duplicated instructions in superscalar processors,” IEEE Transactions on Reliability, Vol.

H. El-Maleh et al. It is estimated that molecular electronics can achieve very high densities (1012 devices per cm2 ) and operate at very high frequencies (of the order of THz) [1]. Several successful nano-scale electronic devices have been demonstrated by researchers, some of the most promising being carbon naotubes (CNT) [2], silicon nano-wires (NW) [3,4], and quantum dot cells [5]. It has been shown that using self-assembly techniques, we can overcome the limitations posed by lithography for the smallest feature size [1].

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