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By Noel M. Morris (auth.)

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Sample text

And may have a value from about 1 ns to a fraction of a microsecond. Values for typical logic families are given in chapter 5. 13. The first of these methods is to shunt the input resistor R with a speed-up capacitor C. This allows the total input voltage transition to be momentarily applied to the base of the transistor. Thus, when signal A changes from zero to a positive voltage, the capacitor charging current causes a momentary rush of current to be applied to the transistor base, so reducing the delay time.

When either or both of the inputs are logic '1 ',the current in R 1 is increased and that in R 2 is reduced. Since TR1 and TR2 are connected in a wired-0 R configuration, the output at the collector of TR 1 is A. 8 which, by De Morgan's theorem, is A+ 8, that is, the NOR function of the inputs. As a result of the action described above, we see that the logical function at the collector of TR3 is A+ B. l2 A VEE (-5·2V) '--y-----1 emitter follower output stages Fig. 8 An ECL OR/NOR gate The emitter follower stages containing TR4 and TR5 fulfill two functions.

7). 3 are current sourcing gates, since the gate acts as a current source when the output voltage is HIGH. 4, and consists of aD R L AND section followed by an invertor. The function generated at point Y is the AND function of inputs A and 8, and is inverted by the transistor output stage. ---, Ds X I I I to other diodes : - - - fan- In expander ___________ _! Fig. 4 A DTL NAND gate When either input A or input 8 is logic '0', the circuit designer must ensure that the current flowing in R 1 chooses to flow through the appropriate input diode (DAor D 8 ), rather than through D1 and D2.

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