By David K. Fibush
1994 1st Tektronix. 4to., 82pp., wraps. VG.
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Extra info for A Guide to Digital Television Systems and Measurements
CCIR-656 – The physical parallel and serial interconnect scheme for CCIR-601. CCIR 656 defines the parallel connector pinouts as well as the blanking, sync, and multiplexing schemes used in both parallel and serial interfaces. Reflects definitions in EBU Tech 3267 (for 625-line signals) and in SMPTE 125M (parallel 525) and SMPTE 259M (serial 525).
Figure 8-1 shows how the recovered signal can be as perfect as the original if the data is detected with a jitter-free clock. As long as the noise and jitter don’t exceed the threshold of the detection circuits (that’s, the eye is sufficiently open) the data will be perfectly reconstructed. In a practical system, the clock is extracted from the serial bit stream and contains some of the jitter present in the signal. Jitter in the clock can be a desirable feature to the extent that the jitter helps position the clock edge in the middle of the eye.
As explained above, the DAC clock jitter requirements are considerably tighter. A draft AES/EBU standard specifies the DAC clock at 1 ns jitter. 1 ns. The important point is that receivers for AES/EBU serial audio should be designed to handle up to 40 ns of jitter, whereas the internal DAC circuitry of such receivers must reduce the clock jitter to an acceptable level. The situation for parallel digital video is similar; however, practical implementations have generally avoided the whole issue.